Code coverage and function coverage tells the verification engineer if the test plan goals have been met or not.
Thare are following types of code coverage :
1. Line Coverage
2. Toggle Coverage
3. FSM Coverage
4. Combinational coverage
1. Line Coverage :
Line coverage is answer the the simple question whether this line is covered or not. It is recommended that the line coverage for all modules in a design receive 100% coverage. If a line of logic is not executed during simulation, the design has not been fully exercised. Line coverage is useful for determining holes in the test suite.
2. Toggle Coverage :
Toggle Coverage is answer to the question "Did this bit of register or wire changed from 0 to 1 and 1 to 0 during simulation". A bit is covered if it changes from 0 to 1 and 1 to 0 during simulation.
For a design to pass full coverage, it is recommended that the toggle coverage for all modules in a design received 100% coverage. If a bit is never changes value, it is usually an indication that a mode is not being exercised in the design or a datapath has a stuck-at issue.
3. Combinational Coverage:
Combinational logic coverage answers the question, "What values did an expression (or subexpression) evaluate to (or not evaluate to) during the course of the simulation?"
This type of coverage is extremely useful in determining logical combinations of signals that were not tried during simulation, exposing potential holes in verification.
assign c = a I b;
The expression "a | b" can result in two values, 0 and 1, but can do so in four combinations:
- a = 0, b = 0, c = 0
- a = 0, b = 1, c = 1
- a = 1, b = 0, c = 1
- a = 1, b = 1, c = 1
Noticing the values assigned to a and b during simulation, shows that combinations (2) and (4) were hit during execution while combinations (1) and (3) were not (2 out of 4 - 50%).
it is recommended that the combinational logic coverage for all modules be 80% or higher. If the expression coverage for an expression is not 100%, it is recommended that the verification engineer closely examine these missed cases to determine if more testing is required. Sometimes certain combinations of signals are unachievable due to design constraints, keeping the expression coverage from ever reaching a value of 100% but still can be considered fully covered.
4. Finite State Machine (FSM) Coverage:
Finite state machine (FSM) coverage answers the question, "Did I reach all of the states and traverse all possible paths through a given state machine?"
There are two types of coverage detail for FSMs that Covered can handle:
- State coverage - answers the question "Were all states of an FSM hit during simulation?"
- State transition coverage - answers the question "Did the FSM transition between all states (that are achievable) in simulation?"
It is recommended that the FSM coverage for all finite state machines in the design to receive 100% coverage for the state coverage and 100% for all achievable state transitions. Since Covered will not determine which state transitions are achievable, it is up to the verification engineer to examine the executed state transitions to determine if 100% of possible transitions occurred.